Pica: A MIMD Architecture for Multi-Node Chip Implementation

VLSI technology continues to improve chip density, size, and speed. In the near future, multi-node chips will ooer the only avenue to eeciently harness these increasing resources. Limited oo-chip bandwidth and local memory requirements are two obstacles to multi-chip MIMD nodes. This paper introduces Pica, a ne-grain, message-passing architecture design to overcome these limitations. Using recent developments in epi-taxial liftoo and deposition of optoelectronic devices and through-chip transmission, a network is presented that provides a high-bandwidth optoelectric communication medium that scales with the circuit feature size. This network employs a ooset cube topology. To support multi-node chips, a low-memory approach to execution is adopted where high I/O bandwidth replaces large local memories. The Pica machine architecture provides support for ne-grain tasks (< 30 instructions) via low-latency communication , fast task switching, low-cost synchronization, and eecient storage and task management. These mechanisms are supported by novel architectural features including a xed-length context length for storage management, a context cache replacing the typical register le, task management hardware which provides single cycle context swaps, and hardware synchronization support in the datapath.